[J-core] Updated the github a bit.

D. Jeff Dionne jeff at coresemi.io
Thu Oct 10 23:05:38 EDT 2019

On Oct 10, 2019, at 22:24, Joh-Tob Sch├Ąg <johtobsch at gmail.com> wrote:
> Not sure if this is the right place to talk about this but it would be great if there was a short tutorial on how to put your own code in to the RAM/ROM img.

Ok, sure can do!  Give me a day or two, we have an eXecute In Place from SPI flash block that changes the linker scripts etc.

> I played with it in the past but was not successful. I also failed to follow the makefiles.

Ok, NP.  I assume you want a bare metal tutorial... the linux executable side has no special tricks to it.


>> On Thu, 10 Oct 2019 at 23:33, Rob Landley <rob at landley.net> wrote:
>> FYI we converted the instruction decoder from a microcode lookup table in ROM to
>> a VHDL if/else staircase, and now we're collapsing together redundant entires in
>> the if/else staircase to get the code size down and show us what else we can
>> optimize.
>> A lot of the cleanups we're doing to the code are things the Lattice optimizer
>> is already finding, but not all of them, and getting it all collated helps us
>> see where can shuffle muxes around and such to make it smaller.
>> The original reason we started doing the if/else staircase version was because
>> that's what you need to make an ASIC anyway, and it turns out to be easier for
>> software developers to read and understand. :)
>> When we're done with the instruction decoder (pipeline stage 2), there are
>> potential cleanups in the execution engine (pipeline stage 3). (We already did
>> one but Jeff refused to upload it to github when I asked him, I'll probably have
>> to redo it.)
>> Rob
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