[J-core] Updated the github a bit.

Joh-Tob Sch├Ąg johtobsch at gmail.com
Thu Oct 10 22:24:05 EDT 2019

Not sure if this is the right place to talk about this but it would be
great if there was a short tutorial on how to put your own code in to the
RAM/ROM img. I played with it in the past but was not successful. I also
failed to follow the makefiles.

On Thu, 10 Oct 2019 at 23:33, Rob Landley <rob at landley.net> wrote:

> FYI we converted the instruction decoder from a microcode lookup table in
> ROM to
> a VHDL if/else staircase, and now we're collapsing together redundant
> entires in
> the if/else staircase to get the code size down and show us what else we
> can
> optimize.
> A lot of the cleanups we're doing to the code are things the Lattice
> optimizer
> is already finding, but not all of them, and getting it all collated helps
> us
> see where can shuffle muxes around and such to make it smaller.
> The original reason we started doing the if/else staircase version was
> because
> that's what you need to make an ASIC anyway, and it turns out to be easier
> for
> software developers to read and understand. :)
> When we're done with the instruction decoder (pipeline stage 2), there are
> potential cleanups in the execution engine (pipeline stage 3). (We already
> did
> one but Jeff refused to upload it to github when I asked him, I'll
> probably have
> to redo it.)
> Rob
> _______________________________________________
> J-core mailing list
> J-core at lists.j-core.org
> http://lists.j-core.org/mailman/listinfo/j-core
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.j-core.org/pipermail/j-core/attachments/20191011/e1a1eb84/attachment.html>

More information about the J-core mailing list