[J-core] Porting J1 to LiteX

[Rob Landley]

On 6/13/21 2:01 AM, William D. Jones wrote:
> 1. The repo as-is came with a bootrom that's already been converted to a 
> VHDL array. Where is the bootrom C code so I can study it? I want to 
> test some startup code, and this simple SoC seems like a good place as 
> any. In addition, where is the tool that converts it to a VHDL array?

https://github.com/j-core/bootrom

> As an aside, there is a tool called icebram that enables one to write 
> firmware for FPGA BRAMs without recompiling the bitstream. It doesn't 
> directly support VHDL arrays as input, however (it needs a Verilog-style 
> hex file). So maybe I could add support for that too.

Cool!

> 2. Does a classic Wishbone bus adapter exist for J1? LiteX uses the 
> Wishbone bus, so I will need to write an adapter if one doesn't exist. 
> This isn't exceptionally difficult in theory. I'll probably have a 
> harder time getting simulation between Verilog/migen and VHDL to play 
> nice if I'm honest :).

That's a Jeff question, but I'm guessing we haven't written one yet? (We did an
spi bus for the ice40 stuff somewhere. The j2 has a lot more various I/O devices
and stuff like
https://github.com/j-core/jcore-soc/tree/master/components/ring_bus in the tree,
but "wishbone" isn't ringing a bell...)

> 3. LiteX CPUs tend to have variants. Has a multicycle multiplier for J1 
> (not J1sec) been proposed?

Yes, but not implemented yet.

> I imagine this would help both with LUT usage 
> and timing closure. While the ice40 FPGAs aren't particularly fast (with 
> UP5K being particularly slow), I've noticed that J1 has slower max 
> frequency than other LiteX CPUs. I don't have any particular insights as 
> to "why" however.

Jeff does, and has plans to restructure stuff, but they're contingent on funding
engineering time...

> This is something that Tim and I have wanted to happen for a while, so 
> I'm excited to see if I can get SuperH to work in LiteX!

Cool.

> Sincerely,

Rob