[J-core] Porting J1 to LiteX

[D. Jeff Dionne]

On Jun 13, 2021, at 3:01, William D. Jones <wjones at wdj-consulting.com> wrote:

> The main difference between the UP5K and HX8K SoCs is that UP5K uses the DSPs, and SPRAMs, and passes timing at 12MHz, while the HX8K instantiates the single cycle multiplier in LUTs, uses no SPRAMs, and passes timing at about 31.5MHz.

But does it fit reasonably?  I had found that J1 was impractical in HX, and so did not investigate further.

> 1. The repo as-is came with a bootrom that's already been converted to a VHDL array. Where is the bootrom C code so I can study it? I want to test some startup code, and this simple SoC seems like a good place as any. In addition, where is the tool that converts it to a VHDL array?

Yeah, the bootrom repo that Rob pointed you at.  There is a need to separate that into a bare metal runtime... it's on the ToDo, for now another place to look is here: https://github.com/j-core/j-core-ice40/tree/master/testrom which while less clean, is closer to what you'll need.

> 2. Does a classic Wishbone bus adapter exist for J1? LiteX uses the Wishbone bus, so I will need to write an adapter if one doesn't exist. This isn't exceptionally difficult in theory. I'll probably have a harder time getting simulation between Verilog/migen and VHDL to play nice if I'm honest :).

It doesn't exist at the moment.  It should not be hard... keep in mind that J1 is still a full Harvard machine, so you'll need to mux it down to a single master.  The repo has that (simple) logic, just stall fetch until you complete any pending access on the data side (as a first pass).

> 3. LiteX CPUs tend to have variants. Has a multicycle multiplier for J1 (not J1sec) been proposed?

Yes, there are a few proposals... just microcode, only SH1 instructions (no MAC or other DSP functions).  We've also just not had the focus.

> I imagine this would help both with LUT usage and timing closure.

I don't think timing closure, on FPGA multipliers tend to be very fast.  There are a few critical paths, the one that erks me is the T bit feeding into the microcode sequencer.  But when I wrote the MAC unit, it was very clean, even if it's picked up a bit of cruft since.

> While the ice40 FPGAs aren't particularly fast (with UP5K being particularly slow), I've noticed that J1 has slower max frequency than other LiteX CPUs.

IIRC, some are instruction chewers.  J1 is a highly encoded and more complex operation per instruction ISA, and pipelined machine with parallel ALU, MAC and shift units.  The throughput might be comparable, even at a slower clock :)

> I don't have any particular insights as to "why" however.

J.
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