[J-core] Porting J1 to LiteX

[William D. Jones]

Hello all,

As a "weekend" diversion, I'm attempting to port the J1 CPU available at 
https://github.com/j-core/jcore-j1-ghdl to the LiteX SoC Builder: 
https://github.com/enjoy-digital/litex. With it's good code density, a 
core like J1 will fit in just fine to the LiteX ecosystem, and will get 
access to a large number of peripheral cores to boot!

Right now, I am learning VHDL for this project (The Designer's Guide to 
VHDL is helping a lot here), and I've managed to get the GHDL repo to 
compile for ICE40HX8K parts using a dev board I have on hand. The LEDs 
are blinking, so I believe the core is working. My fork is available 
here: https://github.com/cr1901/jcore-j1-ghdl/tree/hx8k. My changes are 
basically to make the source compile for both UP5K and HX8K parts. I did 
not include a testbench for HX8K, as my intent is to start porting J1 to 
LiteX ASAP.

The main difference between the UP5K and HX8K SoCs is that UP5K uses the 
DSPs, and SPRAMs, and passes timing at 12MHz, while the HX8K 
instantiates the single cycle multiplier in LUTs, uses no SPRAMs, and 
passes timing at about 31.5MHz.

Before I begin the LiteX port, I have a few questions. Okay, many 
questions :). But let's start with the most important ones:

1. The repo as-is came with a bootrom that's already been converted to a 
VHDL array. Where is the bootrom C code so I can study it? I want to 
test some startup code, and this simple SoC seems like a good place as 
any. In addition, where is the tool that converts it to a VHDL array?

As an aside, there is a tool called icebram that enables one to write 
firmware for FPGA BRAMs without recompiling the bitstream. It doesn't 
directly support VHDL arrays as input, however (it needs a Verilog-style 
hex file). So maybe I could add support for that too.

2. Does a classic Wishbone bus adapter exist for J1? LiteX uses the 
Wishbone bus, so I will need to write an adapter if one doesn't exist. 
This isn't exceptionally difficult in theory. I'll probably have a 
harder time getting simulation between Verilog/migen and VHDL to play 
nice if I'm honest :).

3. LiteX CPUs tend to have variants. Has a multicycle multiplier for J1 
(not J1sec) been proposed? I imagine this would help both with LUT usage 
and timing closure. While the ice40 FPGAs aren't particularly fast (with 
UP5K being particularly slow), I've noticed that J1 has slower max 
frequency than other LiteX CPUs. I don't have any particular insights as 
to "why" however.

This is something that Tim and I have wanted to happen for a while, so 
I'm excited to see if I can get SuperH to work in LiteX!

Sincerely,

-- 
William D. Jones
wjones at wdj-consulting.com