[J-core] List of J-cores

[D. Jeff Dionne]

On Jun 12, 2021, at 15:24, Pär Moberg <ghostdewolf at gmail.com> wrote:

> Hi,

Hi.

> I would like to know of the current state of the different J-cores.

What you can get right now.

J1: Runs on very low end FPGAs.  Intended for microcontroller replacement use where you might use AVR, Cortex-M.  Simple build, uses GHDL + Yosys + NextPNR.  GCC bare metal toolchain, all internal memory and external SPI Flash.  WiP: XiP from SPI Flash.

J1sec: J1 with hardware crypto engines.  Security (co)processor.
- Working on integration testing.

J2: Runs on mid size FPGA.  Intended for Linux applications.
Options:
- All internal memory or DDR/LPDDR RAM.  SPI Flash boot.
- Non cached, Instruction Prefetch, or separate I & D cache.

J2SMP: Runs on large FPGAs.  Intended for Linux embedded and signal processing.
- Linux (tracking mainline) running in mission critical application for many years.
- Separate I & D cache, DDR/LPDDR memory.
- Very mature, used in production devices.

J32 / J32SMP: Runs on large FPGAs.  Intended for Linux used as a network or application processor or for embedded systems
- Separate I & D cache, DDR/LPDDR memory.  Full MMU.
- RTL complete, extensive test vectors.
- Linux port incomplete.

There are other versions that are still in development, like the very small J0 (3 stage pipeline) and a multi-issue / out of order J32.  We're still working on those.

J.

> 
> What I would like to know is if they can run Linux?
> 
> What are the planed cores planed capabilities?
> 
> //Pär
> 
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