[J-core] We have started!

D. Jeff Dionne jeff at coresemi.io
Mon Mar 16 02:57:45 UTC 2020

Forgot to attach this inital, quick and dirty synthesis report

2.52. Printing statistics.

=== cpu ===

   Number of wires:              10384
   Number of wire bits:          16211
   Number of public wires:       10384
   Number of public wire bits:   16211
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11281
     CCU2C                         199
     L6MUX21                      1087
     LUT4                         6745
     MULT18X18D                      2
     PFUMX                        2156
     TRELLIS_DPR16X4                32
     TRELLIS_FF                   1060


On 月, 3月 16, 2020 at 11:56 午前, D. Jeff Dionne 
<jeff at coresemi.io> wrote:
> I did a quick feasibility check of the CPU with GHDL synth and yosys, 
> it looks like the 45k gate device would be better for a full SMP 
> system with DDR RAM.  The GHDL and Yosys tool flow is getting pretty 
> good now, but we've still not managed to get a bitstream out of it 
> and nextpnr for somehting meaningful... rapidly advancing though.
> The sticking point for this board is the SDRAM... J-Core memory 
> controller only supports DDR, DDR2 and LPDDR.  There are a few boards 
> with this issue that J-Core could support if we were to write a 
> simple SDRAM controller, or I suppose we could bolt someone else's 
> on.  Still a bit of work to teach the SoC generator how to connect 
> the bus bridges and cache controllers.
> J.
> On 日, 3月 15, 2020 at 11:44 午後, Goran Mahovlić 
> <goran.mahovlic at gmail.com> wrote:
>> Hopefully someone will now port J-CORE to ULX3S
>> https://www.crowdsupply.com/radiona/ulx3s
>> 12F should be more then enough!
>> We already have Litex linux and SaxonSoc linux samples
>> https://twitter.com/lawriegriffiths/status/1238030666719207425
>> Goran
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