[J-core] We have started!

D. Jeff Dionne jeff at coresemi.io
Mon Mar 16 02:56:22 UTC 2020

I did a quick feasibility check of the CPU with GHDL synth and yosys, 
it looks like the 45k gate device would be better for a full SMP system 
with DDR RAM.  The GHDL and Yosys tool flow is getting pretty good now, 
but we've still not managed to get a bitstream out of it and nextpnr 
for somehting meaningful... rapidly advancing though.

The sticking point for this board is the SDRAM... J-Core memory 
controller only supports DDR, DDR2 and LPDDR.  There are a few boards 
with this issue that J-Core could support if we were to write a simple 
SDRAM controller, or I suppose we could bolt someone else's on.  Still 
a bit of work to teach the SoC generator how to connect the bus bridges 
and cache controllers.


On 日, 3月 15, 2020 at 11:44 午後, Goran Mahovlić 
<goran.mahovlic at gmail.com> wrote:
> Hopefully someone will now port J-CORE to ULX3S
> https://www.crowdsupply.com/radiona/ulx3s
> 12F should be more then enough!
> We already have Litex linux and SaxonSoc linux samples
> https://twitter.com/lawriegriffiths/status/1238030666719207425
> Goran
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