[J-core] Did you notice the github?
D. Jeff Dionne
Jeff at SE-Instruments.com
Mon Sep 9 21:27:15 EDT 2019
Ultra scale FPGAs can reach perhaps 150MHz, but this is for development or deployment in small quantities. SEI uses SMP systems on Kintex 7 in commercial products, at 100MHz, sort of a price/performance sweet spot for certain types of applications. Signal processing stuff.
We expect to hit interesting speeds in ASIC mid 2020 timeframe on the roadmap, but let’s see... :)
Rich Felker demonstrated GCC running on a dual core 66MHz J-Core device (on linux of course) a few years ago. It wasn’t exactly... unusable ;) So 1999, un surprisingly.
On Sep 9, 2019, at 21:16, Joh-Tob Schäg <johtobsch at gmail.com> wrote:
>> Like a laptop.
> I do not think 2 J-Cores clocked at 25Mhz is powerful enough to make a
> good laptop. Also Laptops have a lot of components which have nothing
> to do with the CPU and giant circuit boards. Lot's of overhead.
> Even a PDA would need to much unrelated hardware i guess. J-Core is
> going to stay in embedded systems or in calculators like Jeff eluded
> to with Free42 for some time i speculate.
> Making a Gameboy style mobile console might be possible too but we
> could run any existing SEGA games since all the SEGA hardware had
> graphics co-processors which seem out of scope for J-Core.
>> Does the ICE40 port mean you have an open FPGA compiler working?
> Well it depends on what do you mean with compiler.
> This git repo has support or GHDL which allows to compile a simulator.
> If you want do synthesis (generate bit-stream for hardware) the only
> open source tool i know is Yosys and this is currently not supported
> (no options in make file). Getting J-Core to run on ICE40 requires
> proprietary software for now but we target a platform where it is
> possible to have open source tools.
> Jeff, Rob correct me if i am wrong.
> J-core mailing list
> J-core at lists.j-core.org
More information about the J-core