[J-core] Did you notice the github?

Rob Landley rob at landley.net
Thu Sep 12 23:17:57 EDT 2019

On 9/9/19 8:27 PM, D. Jeff Dionne wrote:
> Ultra scale FPGAs can reach perhaps 150MHz, but this is for development or deployment
> in small quantities.  SEI uses SMP systems on Kintex 7 in commercial products, at
> 100MHz, sort of a price/performance sweet spot for certain types of applications.
>  Signal processing stuff.

Our roadmap includes a number of performance improvements, including dual issue
(I.E. executing 2 instructions per clock cycle, which Hitach's SH4 did), further
cache improvements (we removed prefetch to add L2 cache, but the two should be
combined, and eventually we'd want L2 cache), and a pending instruction parser
rewrite that should let us clock the chip noticeably faster even on FPGA.

But of those, only the front end rewrite doesn't make the chip _bigger_, and
we're focusing on "smaller" first. (The rest is J64 territory.)

An ASIC implementation done on a modern process should be able clock
significantly faster than FPGA in general, but there's more design work to do
before committing it to silicon, and our first ASIC is aimed at the "small and
cheap" end of things, not the "big and powerful" end of things. :)

But you _can_ do desktops and phones and stuff with j-core. This instruction set
did game consoles in the 90's.

> We expect to hit interesting speeds in ASIC mid 2020 timeframe on the roadmap, but let’s see... :)
> Rich Felker demonstrated GCC running on a dual core 66MHz J-Core device (on linux
> of course) a few years ago.  It wasn’t exactly... unusable ;)  So 1999, un surprisingly.

Actually the main limiting factor on that was our sd card implementation being
very slow, because it was using mmc bus not sd 1.0 due to patent restrictions.
But the sd 1.0 spec's patents just expired, so we should be able to speed that
up nicely in the near future. :)

> On Sep 9, 2019, at 21:16, Joh-Tob Schäg <johtobsch at gmail.com> wrote:
>>> Like a laptop.
>> I do not think 2 J-Cores clocked at 25Mhz is powerful enough to make a
>> good laptop. Also Laptops have a lot of components which have nothing
>> to do with the CPU and giant circuit boards. Lot's of overhead.
>> Even a PDA would need to much unrelated hardware i guess. J-Core is
>> going to stay in embedded systems or in calculators like Jeff eluded
>> to with Free42 for some time i speculate.

In the short term yes, but not forever. There's no reason you _can't_ make this
design fire breathing.

>> Making a Gameboy style mobile console might be possible too but we
>> could run any existing  SEGA games since all the SEGA hardware had
>> graphics co-processors which seem out of scope for J-Core.

GPUs exist and are a patent minefield, but you could presumably drive an
existing GPU with j-core. And we've got a pipelined DSP design that goes some
way into that space already...

>>> Does the ICE40 port mean you have an open FPGA compiler working?

Not yet, we're using Lattice's compiler at the moment. We have plans, but
there's some work to do and we're figuring out what to prioritize now we've got
the band back together.

>> Well it depends on what do you mean with compiler.
>> This git repo has support or GHDL which allows to compile a simulator.
>> If you want do synthesis (generate bit-stream for hardware) the only
>> open source tool i know is Yosys and this is currently not supported
>> (no options in make file). Getting J-Core to run on ICE40 requires
>> proprietary software for now but we target a platform where it is
>> possible to have open source tools.
>> Jeff, Rob correct me if i am wrong.

This area got weird recently, I'll leave it to Jeff. (tl;dr: more people than we
expected are already working on this, especially on the GHDL side, but the
author of Yosys went to work for a company making a proprietary VHDL library and
there's politics now...)


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