[J-core] Updated the github a bit.

[D. Jeff Dionne]

On Oct 10, 2019, at 17:33, Rob Landley <rob at landley.net> wrote:
> 
> The original reason we started doing the if/else staircase version was because
> that's what you need to make an ASIC anyway, and it turns out to be easier for
> software developers to read and understand. :)

;^} I’m not sure it’s easier to understand, but it certainly is easier (or maybe possible) to quickly hack on.  All of the microcode implementations (simple if/else, reverse aka PLA like, ROM...) come out of a generator tool that reads microcode from the master ISA spreadsheet.  Unfortunately, that tool is written in cloture, and is hard to maintain for mere mortals...  and we have (especially J32) outgrown the tool.

The simple J1 implementation is a good place for some experiments like this... as Rob has said, the synthesis tools are not as bad as we expected at logic optimization for a big mess of statements like this, but structurally there is still things to learn.  It’s pretty clear to me that a PLA like implementation, derived from a higher level ‘microcode assembler’ type input is still where we need to end up.  Large parts of instruction groups are regular and collapse into small pipeline control differences.

Interesting work... Rob’s simple low hanging fruit clean up of the if/else reduced the size to something much closer to the pre-decode + expand logic of the ROM version.  Our 180nm trial synthesis versions are all using the PLA style... we should rerun that analysis.

Cheers,
J