[J-core] Updated the github a bit.

[Rob Landley]

FYI we converted the instruction decoder from a microcode lookup table in ROM to
a VHDL if/else staircase, and now we're collapsing together redundant entires in
the if/else staircase to get the code size down and show us what else we can
optimize.

A lot of the cleanups we're doing to the code are things the Lattice optimizer
is already finding, but not all of them, and getting it all collated helps us
see where can shuffle muxes around and such to make it smaller.

The original reason we started doing the if/else staircase version was because
that's what you need to make an ASIC anyway, and it turns out to be easier for
software developers to read and understand. :)

When we're done with the instruction decoder (pipeline stage 2), there are
potential cleanups in the execution engine (pipeline stage 3). (We already did
one but Jeff refused to upload it to github when I asked him, I'll probably have
to redo it.)

Rob