[J-core] Adding d/i cache to microboard?

Rich Felker dalias at libc.org
Mon Oct 24 11:33:32 EDT 2016

Thanks! That fixed the problem. Performance is worse than mimas_v2, as
expected, since the board target hasn't been updated since everything
was 31.25 MHz, but everything seems to be working fine.


On Mon, Oct 24, 2016 at 01:25:51PM +0900, Osamu Nishii wrote:
> Rich-san
> I found that "Makefile is not generated by soc_gen";
>  (they are manually written files)
> [boards] $ fgrep lpddr microboard/Makefile
> microboard/Makefile:        DDR_TYPE=lpddr \
> This controls boot/dev/ddr.c behavior.
> When replace ddr controller to new one,
> DDR_TYPE should be lpddr2 (instead of lpddr).
> (note: here, lpddr lpddr2 does not link to memory device, but
>   ddr controller.  lpddr2 is for new ddr ctrl (components/ddr2);
>   CL=3).
> When CL=2/3 does not match, OS will not boot.
> I have not synthesized microboard with this modification.
> Just as a comparison, lpddr2 is better.
> Osamu Nishii
> On 2016/10/24 11:02, Rich Felker wrote:
> >As an exercise to learn a bit about soc_gen and stuff, I tried
> >enabling d/i cache for the old microboard target. Just adding the
> >cache_ctrl and changing:
> >
> >-                "ddr_ram_mux" {:architecture "one_cpu_direct"}
> >+                "ddr_ram_mux" {:configuration "ddr_ram_mux_one_cpu_idcache_fpga"}
> >
> >produced errors at soc_gen time, so I tried switching to the new ddr
> >controller too, with the attached patch copied from similar changes to
> >mimas_v2, but the board just reboots as soon as the bootloader jumps
> >from sram to the loaded vmlinux. Any idea what I did wrong?

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