[J-core] nvc and j-core project RTL

D. Jeff Dionne Jeff at SE-Instruments.com
Sun Jun 12 18:56:01 EDT 2016


Here is the diff of the hacked CPU sources used with nvc against the latest mercurial tree.  A few other things have changed which should be of no consequence, hand edited out.  Notice that there are 3 categories of things different:

- there is a work around for master_temp_i variable assignment.  This is/was surely an nvc bug, likely the first thing to retest and/or fix.

- decode_core is looking for generics, which are supplied by hand in the nvc version instead of using configurations.  The register file is looking to pick an implementation based on configuration, but instead the nvc sources have a portable version just manually copied in.

- ieee.math.real and ieee.std_logic_unsigned seem to be missing from nvc’s standard libraries.  Getting a complete set of the IEEE libraries is a problem, because the (commercial) owner of vhdl.org has taken the sources down.  Affects the IEEE.proposed libraries as well, the build target of nvc for those now fails.

J.

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> On Jun 12, 2016, at 11:36 PM, D. Jeff Dionne <Jeff at SE-Instruments.com> wrote:
> 
> On Jun 12, 2016, at 01:53, Rob Landley <rob at landley.net> wrote:
>> 
>> Anybody wanna try feeding the full j2 SOC (not just the stripped down j1 without peripherals) into nvc and see what breaks? :)
> 
> I would bet on 'configurations'.   They are a rather obscure (why?) vhdl construct.  It seems most RTL engineers just make entities of only one implementation, and don't use the configuration language feature to select different implementations, e.g. Spartan 6, inferred or simulation.  A lot of proprietary tools have problems with this, at least in older revisions.
> 
> The soc infrastructure and decoder selection uses this construct.
> 
> J
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