[J-core] Generate myHDL version of j-core

[Daniel V]

Hi!

A thing worth considering, is to automatically generate myHDL versions
of j-core.

myHDL code can be used to develop and test hardware designs in Python code.

VHDL has a huge drawback regarding how it's traditionally used. The
common work-flow in the industry, is to write your hardware in VHDL
and to write test benches in VHDL that generates static stimuli to
generate signal diagrams to look at.

myHDL makes it possible to design and test hardware in Python code
only. And the myHDL part of your Python code, is then used to
automatically generate VHDL or Verilog code, for further testing, or
generation of a bitstream for you FPGA, or for making an ASIC. And
myHDL is well tested, and has been used for making several ASIC's.

I think myHDL output would be a great addition to the toolbox, with an
alternative route for testing and designing further digital logic.

And if you can trust the provided benchmarks for myHDL, then the PyPy
Just-In-Time (JIT) compilator for Python, makes hardware simulations
faster than with GHDL.

// Daniel V.