[J-core] PC-relative loads and delay slots
D. Jeff Dionne
Jeff at SE-Instruments.com
Tue Jul 19 14:39:02 EDT 2016
On Jul 19, 2016, at 11:01, Rich Felker <dalias at libc.org> wrote:
> In the SH1/2 manual (rej09b0171) I found that text for the mova
> instruction but not for mov.l/mov.w. For the latter, the manual
> contains the text:
> "The PC points to the starting address of the second instruction after this MOV instruction." (mov.w)
> "The PC points to the starting address of the second instruction after this MOV instruction, but the lowest two bits of the PC are corrected
> to B'00." (mov.l)
> This is page 202 of REJ09B0171-0500O. No mention of branch delay slots is made here so it might be a mistake/omission.
This omission is actually the necessary clarification. It means in the instruction fetch/execution flow. So, therefore, the branch target (for sure).
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