[J-core] [VHDL help request] Could someone explain how J-core uses VHDL configurations?

[Robert Ou]

Hi,

Could someone provide some examples on how J-core is configured using
VHDL configurations? I see quite a bit of code that defines various
configurations with various names, but I couldn't find any code that
actually selects one (e.g. I see cpu_fpga and cpu_sim being defined,
but I can't figure out how code selects one or the other). With GHDL
at least, some configurations (e.g the decode table) seem to be chosen
based on the order of passing filenames to GHDL, which implies to me
that I am definitely doing something very very wrong. I must admit
that I know nothing about "high-level" VHDL and have never even seen
configurations before.

Robert