[J-core] PC-relative loads and delay slots

Geoff Salmon gsalmon at se-instruments.com
Tue Jul 19 13:01:29 EDT 2016

On 16-07-19 11:01 AM, Rich Felker wrote:
> I agree and I would assume this was the motivation for the sh4 change.
> This is a good time to mention that it would be really nice if illegal
> slot instruction and undefined instruction exceptions actually worked.

The illegal slot instruction detection is implemented. I don't know why 
it's not working. Someone will have to look in simulation to see why.

It uses this function to detect instructions that don't belong in delay 

     function check_illegal_delay_slot (code : std_logic_vector(15 
downto 0)) return std_logic is
         -- Check for instructions that assign to PC:
         -- RTE, RTS, JMP @Rm, JSR @Rm, BRAF Rm, BSRF Rm, BF label, BF 
/S label, BT label, BT /S label, BRA label, BSR label, TRAPA #imm
         if ((code(15 downto 12) = "0000" and code(3 downto 2) = "00" 
and code(0) = '1') or (code(15 downto 14) = "10" and code(12 downto 11) 
= "01" and code(8) = '1') or code(15 downto 13) = "101" or (code(15) = 
'1' and code(13 downto 8) = "000011") or (code(15) = '0' and code(13 
downto 12) = "00" and code(4 downto 0) = "01011")) then
             return '1';
             return '0';
         end if;

That may be an incomplete list.

The illegal/undefined instruction test is woefully incomplete.

     function check_illegal_instruction (code : std_logic_vector(15 
downto 0)) return std_logic is
         -- TODO: Improve detection of illegal instructions
         if code(15 downto 8) = x"ff" then
             return '1';
             return '0';
         end if;

We weren't sure how to implement it without a large amount of logic. At 
one point I was trying to generate it from the instruction spreadsheet. 
I forget why that didn't work, or maybe it did work but the result was 
too large. If the instruction space is full enough, it may be easy to 
hand-write the check_illegal_instruction function to cover all the gaps. 
Whatever is preventing the illegal delay slot test from having an effect 
will also probably stop the illegal instruction test as well though.

- Geoff

More information about the J-core mailing list