[J-core] [VHDL help request] Could someone explain how J-core uses VHDL configurations?

Geoff Salmon gsalmon at se-instruments.com
Mon Jul 18 09:16:57 EDT 2016

Hi Robert

All the components should be bound to a specific entity/architecture so 
that the order of the vhdl files doesn't matter.

In soc_top the selection happens by instantiating the configuration 
somewhere up the hierarchy. Usually this is in vhdl generated by soc_gen 
so that the choice can be changed for different boards.

In particular, for the cpu fpga/sim and decode_table, 
soc_top/targets/boards/mimas_v2/soc.vhd instantiates

     cpus : configuration work.one_cpu_fpga
         port map ( ... );

which is defined in soc_top/targets/cpus_one.vhd

configuration one_cpu_fpga of cpus is
   for one_cpu
     for all : cpu_core
       use entity work.cpu_core(arch);
       for arch
         for u_cpu : cpu
           use configuration work.cpu_fpga;
         end for;
       end for;
     end for;
   end for;
end configuration;

That configuration in turn selects the configuration work.cpu_fpga for 
the cpu, which is in soc_top/components/cpu/core/cpu_config.vhd

configuration cpu_fpga of cpu is
   for stru
     for u_decode : decode
       use configuration work.cpu_decode_reverse;
     end for;
     for u_datapath : datapath
       use entity work.datapath(stru);
       for stru
         for u_regfile : register_file
           use entity work.register_file(two_bank);
         end for;
       end for;
     end for;
   end for;
end configuration;

and that selects the configuration to use for the decode component and 
the entity and architecture to use for the register_file.

All of the choice for the cpu-related entities "flows down" from the 
configuration instantiated in soc.vhd. These "configuration ... end 
configuration;" blocks above are called configuration declarations. 
Configuration specifications are another way in vhdl to bind a component 
to a configuration or entity/architecture. With a configuration 
specification you sort of declare a configuration and bind a component 
in an architecture in one step. We don't use these in soc_top because we 
share the configurations amoung a bunch of boards. A configuration 
specification might be useful in a one-off simulation wrapper though.

I've only briefly looked at myhdl-vhdl-verilog-test (very cool by the 
way!) but I think if you changed the line in jcore_unrecord_wrap.vhd from

jcore: cpu port map (


jcore: configuration work.cpu_fpga port map (

then it would pick the decode_table implementation and the order of vhdl 
files wouldn't matter.

- Geoff

On 16-07-18 05:39 AM, Robert Ou wrote:
> Hi,
> Could someone provide some examples on how J-core is configured using
> VHDL configurations? I see quite a bit of code that defines various
> configurations with various names, but I couldn't find any code that
> actually selects one (e.g. I see cpu_fpga and cpu_sim being defined,
> but I can't figure out how code selects one or the other). With GHDL
> at least, some configurations (e.g the decode table) seem to be chosen
> based on the order of passing filenames to GHDL, which implies to me
> that I am definitely doing something very very wrong. I must admit
> that I know nothing about "high-level" VHDL and have never even seen
> configurations before.
> Robert
> _______________________________________________
> J-core mailing list
> J-core at lists.j-core.org
> http://lists.j-core.org/mailman/listinfo/j-core

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