[J-core] PC-relative loads and delay slots

[Robert Ou]

Hi,

What is the correct behavior of PC-relative instructions such as
"mov.l @(disp, PC), Rn" in a branch delay slot? Is this even allowed?
>From my testing, GAS seems to think it is "disp is multiplied by 4 and
added to the address of the mov.l opcode + 2" but J-core seems to
execute it as "disp is multiplied by 4 and added to the address of the
branch target + 2". I discovered this while working on my MyHDL
demonstration, and you can compare the difference in my demonstration
by running the master branch and the branch_delay_test branch.

Robert