[J-core] PC-relative loads and delay slots
dalias at libc.org
Mon Jul 18 09:52:16 EDT 2016
On Mon, Jul 18, 2016 at 02:37:55AM -0700, Robert Ou wrote:
> What is the correct behavior of PC-relative instructions such as
> "mov.l @(disp, PC), Rn" in a branch delay slot? Is this even allowed?
> From my testing, GAS seems to think it is "disp is multiplied by 4 and
> added to the address of the mov.l opcode + 2" but J-core seems to
> execute it as "disp is multiplied by 4 and added to the address of the
> branch target + 2". I discovered this while working on my MyHDL
> demonstration, and you can compare the difference in my demonstration
> by running the master branch and the branch_delay_test branch.
If true I think it's a bug. The original SH ISA documentation
specifies the behavior for "PC-relative" mov instructions as:
"The PC points to the starting address of the second instruction
after this MOV instruction"
(as opposed to the actual current value of the program counter). This
text is found on page 202 of document REJ09B0171-0500O.
I'm quite surprised we haven't run into this bug, since I would expect
gcc to generate code with immediate loads in branch delay slots (e.g.
when making function calls with constant arguments).
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