[J-core] MyHDL+J-core+Verilog demonstration

Robert Ou rqou at robertou.com
Mon Jul 18 05:36:29 EDT 2016


I have managed to hack together a demonstration that drives a J-core
CPU (core only, no AIC or UART or other peripherals) from a MyHDL
master simulation. Notably, I have also managed to hack it together
with some code written in Verilog and have MyHDL+VHDL+Verilog all
running at once in a single simulation. You can check out the code on
GitHub here: https://github.com/rqou/myhdl-vhdl-verilog-test . The
repository also contains some notes about what you will need to
actually run it.


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