[J-core] Online talk on the 16th.

[Rob Landley]

On 7/29/20 12:54 PM, Tim 'mithro' Ansell wrote:
> I haven't had a chance to watch your talk yet but I wanted to mention that
> LiteDRAM can do DDR3 on Spartan 6 FPGAs (and handles all the multi-clocks and
> clock domain crossing stuff for you). You can even use LiteDRAM as a module
> inside your VHDL -- microwatt is already doing
> this @ https://github.com/antonblanchard/microwatt
> 
> LiteDRAM */also/* supports DDR, DDR2 and LPDDR2 on the Spartan 6.
>
> There is also a bunch of current work in LiteDRAM lately to improve performance
> with multi-core RISC-V systems
> -- https://github.com/enjoy-digital/litedram/issues/209
> 
> We will be looking at using LiteDRAM with an open source ASIC DFI implementation
> on SKY130 in the near future.
> 
> Tim 'mithro' Ansell

Jeff took a look at it and had a laundry list of comments, but I'm not competent
to forward them in any detail, but I remember he wanted something with burst
mode and that could do back to back transfers without wait states between them.
(His engineers got our LPDDR2 controller to do all the things he was complaining
this one didn't, but it's  not my area...)

Still, this exists and a proposed better one doesn't currently. In "best
implementation currently available" the last two words do a lot of heavy lifting...

Rob