[J-core] Online talk on the 16th.
Tim 'mithro' Ansell
mithro at mithis.com
Wed Jul 29 17:54:23 UTC 2020
I haven't had a chance to watch your talk yet but I wanted to mention that
LiteDRAM can do DDR3 on Spartan 6 FPGAs (and handles all the multi-clocks
and clock domain crossing stuff for you). You can even use LiteDRAM as a
module inside your VHDL -- microwatt is already doing this @
LiteDRAM *also* supports DDR, DDR2 and LPDDR2 on the Spartan 6.
There is also a bunch of current work in LiteDRAM lately to improve
performance with multi-core RISC-V systems --
We will be looking at using LiteDRAM with an open source ASIC DFI
implementation on SKY130 in the near future.
Tim 'mithro' Ansell
On Mon, 27 Jul 2020 at 21:52, Rob Landley <rob at landley.net> wrote:
> Brian Bartholomew wrote:
> > >
> > I watched the talks, and the progress ie exciting; I didn't know DDR3
> > and ethernet were already implemented.
> 100baseT ethernet and LPDDR2 controller have been implemented for a while.
> Gigabit isn't too hard if you're ok talking to an off the shelf PHY chip.
> controllers are available as a library in some FPGAs we're using, but we
> need to
> do our own implementation that we can make an ASIC out of.
> The problem with DDR3 and gigabit ethernet is is clocking the I/O fast
> We're trying to deploy stuff in cheap FPGAs you can get in bulk for under
> There are fast expensive FPGAs that cost 10 times that, and we have a few
> development, but it's too expensive to deploy anything in, where deploy
> "send to customers" or "expect a larger development community to use".)
> In theory you can have I/O circuitry at the edge of the FPGA clocked way
> than the processor the rest of it's implementing, but then there's clock
> and domain crossing, and still timing closure, and the result's messy. We
> a clock domain crossing for the GPS correlators on spartan 6 (which isn't
> fast as kintex so going at the CPU speed it could only track 3 satellites
> once and we needed 5) and it took weeks to debug.
> In the current SOC, 100baseT is 11 megabytes/second (benchmarked) and SD
> 1.0 is
> 12.5 megabytes/second (before packet overhead anyway, 4 data wires clocked
> at 25
> mhz) and when things match up like that switching just _one_ part to be
> leaves the fast bit spinning its wheels. There's a certain amount of
> needing to
> upgrade multiple parts at once to reach a new balance.
> > But where can I buy all that
> > hardware you featured?
> > Brian
> In theory it's going up on crowdsupply. Mike Tokue (in Tokyo) is handling
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> J-core at lists.j-core.org
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