[J-core] J-Core on new open source SkyWater 130nm PDK?

[Tim 'mithro' Ansell]

Hi!

Is anyone in the J-Core community interested in doing a tape out of J-Core
related IP on the new, fully open source SkyWater 130nm PDK I just
announced? https://github.com/google/skywater-pdk

I gave an in depth talk on what is happening with the PDK and announced a
shuttle program which is free (as in beer) for free (as in freedom)
designs. See https://fossi-foundation.org/2020/06/30/skywater-pdk and
https://youtu.be/EczW2IWdnOM

There will be follow on talks about different aspects of the 130nm process
every month for the rest of the year. See
https://fossi-foundation.org/dial-up/

I think the biggest issue is that J-Core is VHDL and the OpenROAD tooling
uses Yosys which only natively supports Verilog. Maybe the GHDL plugin for
Yosys could work here?

It would be nice to have a diverse set of ISAs being taped out. The RISC-V
people are heavily represented and a bunch of Power people are putting
together teams too.

I don't have any time to lead / organize anything, I'm just throwing the
idea out there.

Keep up the good work!

Tim 'mithro' Ansell
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