[J-core] Synthesis for Silicon?
johtobsch at gmail.com
Tue Sep 10 05:43:42 EDT 2019
> Can you tell me and the community more about this?
> J2 was designed for a mixed signal grid monitor chip, on a TSMC 152nm process. It came in at about 40k gates, and about 0.45mm^2 in this process.
This is just the J2 or including the DSP?
Any estimates for the J1 already?
> How expensive are the fixed and per chip costs?
> Depends on if it's a multi project wafer or a full mask set. 180nm full mask set is about $100k US.
I have no idea what the difference between multi project wafer or a
full mask set is. Can someone explain?
> What clock rates are possible at the targeted node?
> We're still optimizing. We can for sure hit 125MHz in 180nm, and probably 500MHz in 45nm.
Mhh i looked at some processors i could find at the same node.
- the PowerPC 7455 “Apollo 6” was produced with Motorola's 0.18 µm
(180 nm) HiPerMOS and it is said to clock >1GHz.
- the second generation Athlon, the Thunderbird, clocked between 600
MHz to 1.4 GHz and was made using 180nm
- the Celeron Willamette was clocked at 1.7 GHz also produced at 180nm
- the PS2 emotion engine at 294 MHz being a vector processor
For 45nm i could find several x86 chips in the 2~3GHz, a PowerPC at
1.243 GHz and for ARM the OMAP4 at 1.2 and a Samsung Exynos 3110 at
1.0~1.2 GHz. There was also an outlier the z196 which clocked up to
Why is J-Core clocked so much slower at the same node size than
commercial chips which eyed for performance or performance per Watt?
Is it in the ISA or just in your design which does not prioritize performance?
> Not right now, no. The chip SEI was doing was about 1 to 2W power budget. But it had 16 DSP cores and 32 hardware accelerators for power system measurements, and 6 high speed LVDS SERDES.
Are looking into releasing the DSP design too?
Will it under the J-Core name too?
> Cheers. A little vague, but we're getting there.
Any details get the community excited. It is probably good that not
all information is released at once any way.
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