[J-core] Synthesis for Silicon?

D. Jeff Dionne Jeff at SE-Instruments.com
Mon Sep 9 23:36:30 EDT 2019

On Sep 9, 2019, at 22:02, Joh-Tob Schäg <johtobsch at gmail.com> wrote:
> Hello J-Core-Team,
> i recall vaguely that J-Core was/is synthesized for processes which allow it to be made into an ASIC. (I think this how you came up with the 3 cents per chip figure)

Yes, we did a number of synthesis runs for J2.

> Can you tell me and the community more about this?

J2 was designed for a mixed signal grid monitor chip, on a TSMC 152nm process.  It came in at about 40k gates, and about 0.45mm^2 in this process.

> What J-Core family members are interesting for ASIC production? 

We are still making a plan for year 2020, but we think the first device will be something fairly generic, for embedded use.  That design will be completely open.  We are not quite sure yet if it will turn into a device people can buy, or if we'll just do an open design test chip.

> What node would you target today?

We will likely do 152nm, because we already have PLL, RAM blocks and LPDDR IO cells.  The other option is 180nm.  The second chip we would probably target either 55nm or 45nm.

> How expensive are the fixed and per chip costs?

Depends on if it's a multi project wafer or a full mask set.  180nm full mask set is about $100k US.

> Do you have a time line for this?

We are working on that... we should know in a month or so.  But, certainly in 2020.

> How many "ASIC resources" (like Gates, space) do you estimate are needed?

The first device will be fairly small, on purpose.  If we add a GPS baseband and/or DSP to the thing, it will be a little larger.

> What clock rates are possible at the targeted node?

We're still optimizing.  We can for sure hit 125MHz in 180nm, and probably 500MHz in 45nm.

> What tools can you use to make such statements? 

It's a full commercial tool flow, unfortunately.

> Any estimates on power consumption/thermal budget?

Not right now, no.  The chip SEI was doing was about 1 to 2W power budget.  But it had 16 DSP cores and 32 hardware accelerators for power system measurements, and 6 high speed LVDS SERDES.

Cheers.  A little vague, but we're getting there.

> Sincerely Johann-Tobias Schäg 
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