[J-core] Checking in.

D. Jeff Dionne Jeff at SE-Instruments.com
Sat Dec 7 06:24:47 UTC 2019

PPP is a supported protocol (of course) and is easy to get going.

By default, Turtle soft SoC has only a console uart, but it is relatively easy to add as many as you want to any gpio pins.  The in repo choices are UARTlite (compatible) and 16550 (compatible), and there are Linux drivers for both.  I don’t think the 16550 driver has been tested since J2 support changed to device tree... but otherwise there should be no surprises to get going on turtle (SoC and Linux sides).


> On Dec 7, 2019, at 06:11, Goran Mahovlić <goran.mahovlic at gmail.com> wrote:
> Hi, 
> you may want to check things that happened recently on ULX3S that has ESP32
> https://github.com/emard/esp32ppp
> I think they are almost there to get SaxonSOC linux that goes online thru EXP32 using PPP
> Goran
>> On Fri, Dec 6, 2019 at 8:50 PM <wjones at wdj-consulting.com> wrote:
>> While this is on my mind...
>> How many UARTs are available on TurtleBoard? I don't actually plan to use 
>> the Ethernet on my TurtleBoard. Instead, I plan use PPP to connect it to the 
>> Internet (it'll connect a UART to a wifi-enabled board's secondary UART). If 
>> there is only room for one UART plus Ethernet, is it possible to accommodate 
>> my requirement and replace Ethernet with a second UART in the bitstream?
>> The (Net)BSD getty is smart enough to multiplex pppd and login when only a 
>> single UART is available, but I don't believe any Linux getty 
>> implementations have this feature...
>> -----Original Message----- 
>> From: Rob Landley
>> Sent: Thursday, December 05, 2019 11:55 PM
>> To: j-core at lists.j-core.org
>> Subject: [J-core] Checking in.
>> Turtle boards have arrived in Canada and Jeff is taking a few to Japan with 
>> him.
>> I believe he's attending Tron Show and should have at least one with him. We
>> still plan to get them up on crowdsupply early in the new year, but haven't
>> finished all the bitstream bits to support framebuffer and audio and such 
>> yet.
>> (We also switched from lx25 to lx45 this batch, and the ethernet in the
>> bitstream doesn't work because we haven't redone the constraints file yet.
>> Different pinout, the circuitry is being constrained to the wrong part of 
>> the
>> FPGA so the traces are too long and the timing's wrong. All the other I/O 
>> works
>> at least at the smoketest level.)
>> We have a longish todo list for our next engineering sprint, but haven't 
>> managed
>> to coordinate schedules quite yet. We think we've come up with two small
>> extensions to the j-core instruction set that would let us do the fast 
>> fourier
>> transforms needed for realtime GPS acquisition (yay). I should do a writeup 
>> on
>> that, but we want to actually implement it first.
>> I need to completely redo the website but haven't quite opened that can of 
>> worms
>> yet. Still collecting material, such as the start of a writeup on place and
>> route at:
>>   https://landley.net/notes-2019.html#11-11-2019
>> Activity continues behind the scenes. Juggling a lot of balls...
>> Rob
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>> --
>> William D. Jones
>> wjones at wdj-consulting.com 
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