[J-core] Fwd: ISA manual for SH-2

[D. Jeff Dionne]

This https://antime.kapsi.fi/sega/files/h12p0.pdf is probably the best of the legacy Hitachi documentation to look at.  Look specifically at Appendix A starting pg 251 for the encodings, and the table in section A.4 was dropped from later versions.  That table points possible ways to most efficient decoding.

Each of the instructions are also explained in detail (except CAS.L, which is new).  We expect J2 to be a compatible superset, and should test as such (anything else is a bug).  However, J-Core pipeline is a different implementation than any SH, so the instruction timings are also different.  J2 also has separate instruction and data busses, SH2 doesn't.  J2 has a single register file write back port, SH has multiple (likely 2, at least logical) write back ports.  Etc.

Cheers,
J

> On May 25, 2017, at 23:41, Kartik Agaram <ak at akkartik.com> wrote:
> 
> Hi,
> 
> I'm curious what primary documents y'all used in the design of the J-Core architecture and instruction encoding. In particular I'm looking at this link from one of your webpages and wondering if there's a more unpacked/detailed exposition. I did find the book for the SH-4 on Wikipedia. Is there something like that for the SH-2?
> 
> Thanks,
> Kartik
> http://akkartik.name/about
> 
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