<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>This <a href="https://antime.kapsi.fi/sega/files/h12p0.pdf">https://antime.kapsi.fi/sega/files/h12p0.pdf</a> is probably the best of the legacy Hitachi documentation to look at. Look specifically at Appendix A starting pg 251 for the encodings, and the table in section A.4 was dropped from later versions. That table points possible ways to most efficient decoding.</div><div><br></div><div>Each of the instructions are also explained in detail (except CAS.L, which is new). We expect J2 to be a compatible superset, and should test as such (anything else is a bug). However, J-Core pipeline is a different implementation than any SH, so the instruction timings are also different. J2 also has separate instruction and data busses, SH2 doesn't. J2 has a single register file write back port, SH has multiple (likely 2, at least logical) write back ports. Etc.</div><div><br><div>Cheers,<div>J</div></div></div><div><br>On May 25, 2017, at 23:41, Kartik Agaram <<a href="mailto:ak@akkartik.com">ak@akkartik.com</a>> wrote:<br><br></div><blockquote type="cite"><div><div dir="ltr"><div class="gmail_quote"><div dir="ltr">Hi,<div><br></div><div>I'm curious what primary documents y'all used in the design of the J-Core architecture and instruction encoding. In particular I'm looking at <a href="http://www.shared-ptr.com/sh_insns.html" target="_blank">this link</a> from one of your webpages and wondering if there's a more unpacked/detailed exposition. I did find <a href="http://www.st.com/content/ccc/resource/technical/document/user_manual/69/23/ed/be/9b/ed/44/da/CD00147165.pdf/files/CD00147165.pdf/jcr:content/translations/en.CD00147165.pdf" target="_blank">the book for the SH-4</a> on Wikipedia. Is there something like that for the SH-2?</div><div><br></div><div>Thanks,</div><div>Kartik</div><div><a href="http://akkartik.name/about" target="_blank">http://akkartik.name/about</a></div></div>
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