[J-core] Jcore mailing list and tutrle board
D. Jeff Dionne
Jeff at SE-Instruments.co.jp
Fri Jul 7 06:13:33 EDT 2017
On Jul 7, 2017, at 4:07, David Summers <jcore at davidjohnsummers.uk> wrote:
>> Which is why this looks very different. We don't use anything the vendor requires, because that locks in the vendor. The synthesis tools are wrapped in Makefiles, and you can replace them with another toolchain. This is not a Xilinx, S6 (or A7) board. It's a board that happens to use an S6 to carry the J-Core SoC. Some of our customers use K7, it will be available on a TSMC process soon... Nothing we can't replace can be used.
> Confused. Though you had to use Xilinx tools to build the bitsteam. Its going to be hard to escape from using manufacturer tools for converting VDHL/Verilog into something that can program a FPGA (whoever makes it).
Yes, this is true. The point is to not use anything that ties you to the vendor tools, such as hard macro blocks, their JTAG tools, etc. For instance, almost every design that uses DDR memory on Xilinx uses their memory generator tool. We have a complete controller that only uses their DDR I/O cell (which is not a problem to replace on any technology). We have wrappers for just about everything, but still the implementations of things like register files is as portable as possible. None of the tool features are used, if they cause vendor lock.
> But surely this is just a tool for developing j-core devices. And once you go onto an ASIC, you'll be tied to the process that is used for the layout of the ASIC.
No, that is strictly avoided, we are portable RTL just about everywhere. We either design hard macros (LVDS, register files...) or license them (SRAM blocks, PLL) but it has to be generic stuff. e.g. our high speed SERDES transceivers that taped out at 180nm (deep N well process for low noise analog) required a little redesign for 152nm (85% shrink), and SRAM is always a pain. Everything else, we are completely process portable.
> But you will end up witha chip based on an open VHDL, against which it can be to verify how the chip is coded.
But keep in mind I didn't say we don't support JTAG, or that you -can't- use Turtle to develop RTL. The AVR on the Turtle is connected to the JTAG, and you can use it that way if you write a driver for it. We use urjtag and gdbproxy through a JTAG TAP for debug to the J-Core CPUs. It goes through the S6 BSCAN macro block, or you can instantiate an RTL TAP controller and use regular pins. There is no reason you can't use the JTAG program the SPI flash, for instance, should you brick the AVR. I've not had to use a JTAG cable, even for RTL development, for 3-4 years I would guess...
On chip logic debug is easy to do also... just instantiate an on-chip logic analyser. You could connect it directly to the J-Core CPU bus, or even something like this connected to an on chip UART: http://hamsterworks.co.nz/mediawiki/index.php/CheapScope You don't even need a USB UART, just compile the control software to run on the J-Core Linux on the board, ssh over and do your logic debug right on the target...
I think it's important to note, all this stuff is very mature, and in production use. Turtle is an open project, but that doesn't mean that it itself is experimental, all of the circuitry, RTL (J-Core itself, peripherals, DDR, Ethernet...), tools (including the AVR supervisor USB MCU), SW toolchains, uClinux OS, etc. is in daily use in mission critical infrastructure applications. That is why J-Core exists, and also why the open side is slow moving at times... we use it in our day jobs :)
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