[J-core] Adding SH2/SH4 support to LiteX using J-Core?

D. Jeff Dionne Jeff at SE-Instruments.com
Fri Feb 10 00:04:48 EST 2017

On Feb 9, 2017, at 1:15 AM, wjones at wdj-consulting.com wrote:
> Hello Jeff,

Hi William,

> I committed the repo as-is to Github so when I attempt to build MiSoC/LiteX
> designs with J-core I can easily reference the core as a git submodule
> (which is how cores are conventionally referenced in MiSoC/LiteX). There
> have not been any new commits yet, so you are up to date :).

Ok.  Please keep in mind that this is not the j-core repo, the RTL checked in
to your github is a snapshot of post processed files suitable for test synthesis
using new tools.  That is, it’s configured a certain way, and certain of those
files are the output of auto generation tools.  It’s not the sources, it’s
an intermediate output.

> My proposed changes to the copy of my repo (and *only* if necessary) are
> adding the single-cycle multiplier back in (I noticed you said J2 even with
> the MAC fits on an ICE408K... that is very interesting!), and tweaking the
> bus interface to be wishbone-friendly. Though for the latter, nothing stops
> me from doing that on the MiSoC/LiteX side.

These sources have a MAC unit included (contained in mult_pkg.vhd and mult.vhd,
which was auto generated from .vhm sources).  This has a pipelined multiplier
and very wide (64 bit) accumulator, and also saturation logic.  It operates as
a semi autonomous execution unit, off to the side of the rest of the (integer)
pipeline, and therefore includes it’s own state machine.  One could ‘simply’
write a stub that returns 0 on y.mach y.macl and deasserts y.busy to get a
working core without that block.  IIRC, gcc only knows how to generate some of
the instructions that this unit executes.  So, similarily, one could make a
simple block that just does those, perhaps using a generic to select the number
of cycles of latency (that is, the width of the hardware multiplier).

> Compared to J2 proper, with all the peripherals, are there any architectural
> differences besides the lack of single-cycle multiplier? I would like to
> keep my repo copy of the core up to date with upstream changes.

The main J2 repo (SEI internal, as Rob always points out, at the moment) has a
few changes to the co-processor interface, and therefore the AIC.  I think that
for the most part, the RTL, tools, and instruction set are the same as the last
full opensource drop (provided it has CAS.L).


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