[J-core] Adding SH2/SH4 support to LiteX using J-Core?

[D. Jeff Dionne]

Just a (meaningless) FYI:

I used a current version of yosys, built against an eval version of Verific VHDL front end, to synthesise this hacked version of J2 just now. 

It looks like it would fit an ICE40 8k, even with the MAC unit included.

Cheers,
J.

> On Feb 8, 2017, at 19:22, D. Jeff Dionne <Jeff at SE-Instruments.co.jp> wrote:
> 
>> On Feb 7, 2017, at 9:50, <wjones at wdj-consulting.com> <wjones at wdj-consulting.com> wrote:
>> 
>> Per the conversation on IRC, I have created a github mirror with what landley calls the "J1" core: https://github.com/cr1901/jcore-j1
> 
> Hi Will,
> 
> I checked out a copy of this, and it appears like the changes you've made were lost along the way.  The sources are identical to a hacked version of j2 that I provided as a proof of concept for use with NVC.
> 
> I'd be very interested in the changes you've made, if you can check them in...
> 
> Cheers,
> J.
> 
>> The J1, among other small changes compared to J2, does not have a single-cycle multiplier. All of the FPGAs HDMI2USB are using have hardware multipliers, so I may very well patch the core to create a "CPU-core-only" J2 distribution.
>> 
>> I assume J3/J4 would not share the same repo as J2? I think J3/J4 would be a separate port to LiteX/MiSoC.
>> 
>> 
>> From: Tim Ansell
>> Sent: Monday, February 06, 2017 12:14 PM
>> To: j-core at lists.j-core.org
>> Cc: Rob Landley ; wjones at wdj-consulting.com
>> Subject: Adding SH2/SH4 support to LiteX using J-Core?
>> 
>> Hence, I'm really interested in adding "J-Core" / sh2+sh4 support to that list and wanted advice about the best way to approach this problem. As we already have our own set of peripherals (UART, DDR controller, Ethernet, etc) we just want to use the CPU core rather than your full SoC. Do you have any advice on the best way to do this? What would be the best way to extract "just the CPU"?
>> 
>> 
>> Sincerely,
>> 
>> --
>> William D. Jones
>> wjones at wdj-consulting.com 
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>