[J-core] Adding SH2/SH4 support to LiteX using J-Core?

[Max Bruckner]

Am Montag, den 06.02.2017, 09:14 -0800 schrieb Tim Ansell:
> Normally we would use something like Verilator or iVerilog to get the
> basics working (CPU executing instructions and interrupts) in
> simulation, but as J-Core is VHDL there doesn't seem a good FOSS
> option for doing things that way (although I guess we could try
> rqou's co-simulation method[5]).
> 
>  [5]: https://github.com/rqou/myhdl-vhdl-verilog-test

Usually [GHDL](http://ghdl.free.fr) is used for free software VHDL
simulation.
J-Core seems to have some scripts in place to simulate the cpu with
GHDL
already (although I haven't looked at how to use them yet).
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 488 bytes
Desc: This is a digitally signed message part
URL: <http://lists.j-core.org/pipermail/j-core/attachments/20170206/9914dc97/attachment.sig>