[J-core] Adding SH2/SH4 support to LiteX using J-Core?
max at maxbruckner.de
Mon Feb 6 15:57:05 EST 2017
Am Montag, den 06.02.2017, 09:14 -0800 schrieb Tim Ansell:
> Normally we would use something like Verilator or iVerilog to get the
> basics working (CPU executing instructions and interrupts) in
> simulation, but as J-Core is VHDL there doesn't seem a good FOSS
> option for doing things that way (although I guess we could try
> rqou's co-simulation method).
> : https://github.com/rqou/myhdl-vhdl-verilog-test
Usually [GHDL](http://ghdl.free.fr) is used for free software VHDL
J-Core seems to have some scripts in place to simulate the cpu with
already (although I haven't looked at how to use them yet).
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