[J-core] working on SH-2 emulator.

[D. Jeff Dionne]

On Sep 5, 2016, at 1:49 PM, BGB <cr88192 at gmail.com> wrote:
> On 9/4/2016 11:14 PM, D. Jeff Dionne wrote:
>> I second all of that, but with one caveat: qemu doesn't try to be pipeline accurate, and I'm not even sure I know what that means as soon as you are multi issue.  What I think you really mean is ISA internal state consistent, which (unfortunately)  does expose a bit of pipeline state the way the ISA was originally designed.
>> 
>> What I personally would like to see is if someone could take ownership of the test rom, which was originally done by someone who had an itch to scratch ;) and extend it with corner cases...
>> 
> 
> for some of this funkiness, in my case I ended up reordering the instructions in the decoder (so, after decoding, the operation in the delay slot appears before its associated branch instruction).
> 
> I don't know if this is sufficient.

Immediate reaction is this likely doesn't do it, because...

...
> though, there could be other issues, like funky register-dependency semantics or effects on the calculation of PC-relative addresses or similar that I am not presently aware of (I have had a bit of an issue making sense of the exact behavior of PC-relative addressing in this ISA).

This.  There is a long thread on the list here that talks about these issues.  There are instructions that are illegal in the delay slot, and while for the most part, pipeline hazards are taken care of (look at the bypass logic in the register file RTL for instance) at least the PC relative calculations do expose some implementation details, resulting in counter intuitive behaviour.

J.