[J-core] working on SH-2 emulator.
cr88192 at gmail.com
Mon Sep 5 00:49:24 EDT 2016
On 9/4/2016 11:14 PM, D. Jeff Dionne wrote:
> I second all of that, but with one caveat: qemu doesn't try to be
> pipeline accurate, and I'm not even sure I know what that means as
> soon as you are multi issue. What I think you really mean is ISA
> internal state consistent, which (unfortunately) does expose a bit of
> pipeline state the way the ISA was originally designed.
> What I personally would like to see is if someone could take ownership
> of the test rom, which was originally done by someone who had an itch
> to scratch ;) and extend it with corner cases...
for some of this funkiness, in my case I ended up reordering the
instructions in the decoder (so, after decoding, the operation in the
delay slot appears before its associated branch instruction).
I don't know if this is sufficient.
but, as far as I understood the spec when I read it, this was the
I could just as easily make them not be flipped, executing the
delay-slot instruction after the branch, but this does not seem to be
what the spec implies.
though, there could be other issues, like funky register-dependency
semantics or effects on the calculation of PC-relative addresses or
similar that I am not presently aware of (I have had a bit of an issue
making sense of the exact behavior of PC-relative addressing in this ISA).
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