[J-core] Adding d/i cache to microboard?

[Rich Felker]

As an exercise to learn a bit about soc_gen and stuff, I tried
enabling d/i cache for the old microboard target. Just adding the
cache_ctrl and changing:

-                "ddr_ram_mux" {:architecture "one_cpu_direct"}
+                "ddr_ram_mux" {:configuration "ddr_ram_mux_one_cpu_idcache_fpga"}

produced errors at soc_gen time, so I tried switching to the new ddr
controller too, with the attached patch copied from similar changes to
mimas_v2, but the board just reboots as soon as the bootloader jumps
from sram to the loaded vmlinux. Any idea what I did wrong?

Rich
-------------- next part --------------
diff --git a/targets/boards/microboard/design.edn b/targets/boards/microboard/design.edn
index 0ac54d6..7644efc 100644
--- a/targets/boards/microboard/design.edn
+++ b/targets/boards/microboard/design.edn
@@ -132,7 +132,12 @@
                                           "clk90_o" "clk_sys_90"
                                           "clk2x_o" "clk_sys_2x"
                                           "locked" "clock_locked0"}}
-                    "ddr_iocells" {}
+                    "ddr_iocells" {:entity "ddr_phy"
+                                   :configuration "ddr_phy_spartan6"
+                                   :ports {"ck_p" "ddr_clk"
+                                           "ck2x0" "clk_sys"
+                                           "ck2x90" "clk_sys_90"}
+                                   :generics {"READ_SAMPLE_TM" (freq_to_read_sample_tm CFG_CLK_MEM_FREQ_HZ)}}
                     "reset_gen" {:ports {"clock_locked1" 1}}
                     "eth_clk_bufs" {}}
 
@@ -146,11 +151,14 @@
                         :generics {"INSERT_WRITE_DELAY_BOOT_MEM" false
                                    "INSERT_READ_DELAY_BOOT_MEM" false
                                    "INSERT_INST_DELAY_BOOT_MEM" false}}
-                "ddr_ram_mux" {:architecture "one_cpu_direct"}
-                "ddr_ctrl" {:generics {"c_data_width" CFG_DDRDQ_WIDTH
-                                       "c_sa_width" CFG_SA_WIDTH
-                                       "c_dll_enable" 2
-                                       "c_period_clkbus" CFG_CLK_CPU_PERIOD_NS}}}
+                "ddr_ram_mux" {:configuration "ddr_ram_mux_one_cpu_idcache_fpga"}
+                "ddr_ctrl" {:entity "ddr_fsm"
+                            :ports {"clk_2x" "clk_sys_2x"
+                                    "clk" "clk_sys"
+                                    "clk_90" "clk_sys_90"
+                                    "fix_pinhi" 0
+                                    "fix_pinlo" 0}
+                            :generics {"READ_SAMPLE_TM" (freq_to_read_sample_tm CFG_CLK_MEM_FREQ_HZ)}}}
 
  :device-classes
  {$include "../common_device_classes.edn"
@@ -203,4 +211,8 @@
    :generics {"c_addr_width" 11
               "c_buswidth" 32
               "default_mac_addr" 0
-              "ASYNC_BRIDGE_IMPL2" false}}]}
+              "ASYNC_BRIDGE_IMPL2" false}}
+  {:class "cache_ctrl"
+   :base-addr 0xabcd00c0
+   :irq {"int0" {:cpu 0 :irq 3}
+         "int1" {:cpu 1 :irq 3 :dt? false}}}]}