[J-core] qemu updates / roadmap

[Rob Landley]

On 05/17/2016 05:36 PM, Geoff Salmon wrote:
> On 16-05-17 06:15 PM, Rich Felker wrote:
>> See Rob's previous post to this list:
>>
>> http://lists.j-core.org/pipermail/j-core/2016-April/000038.html
>>
>> I think the SRAM part is larger than he stated though; check the VHDL
>> or just use the boot loader linker script as a guide for now.
> It is 32KB. It's all writeable though. There is no ROM/SRAM partition in
> the current FPGA designs.
>
> In an ASIC, there will be a separate ROM holding the bootloader and a
> writeable RAM region which is uninitialized at power on. At some point
> we'll need to implement this same separation between a one-port ROM and
> a RAM in the FPGA to test the data and instructions buses work as
> expected, but we haven't done that yet even though we'll often call it
> the "bootrom".

So the boot code is copied into sram before the processor starts executing?

> If you're curious, the memory is instantiated in the file
> soc_top/tools/memory_fpga.vhd.in. This file is modified by a perl
> script, soc_top/tools/patchcode.pl, which inserts the INIT_NN generics
> into the VHDL to put the bootloader image into the memory.

How does this "put" work...?

It sounds like it creates circuitry that writes a series of values into
the memory before the processor starts, and this is easier for us to do
in the FPGA than make an actual ROM because the FPGA already includes
some sram in its libraries so it's cheap for us to use that, and making
our own ROM with address and data busses that let it be randomly
addressable and readable would eat way more cells than this sequential
writer does?

Rob