[J-core] qemu updates / roadmap
gsalmon at se-instruments.com
Tue May 17 18:36:40 EDT 2016
On 16-05-17 06:15 PM, Rich Felker wrote:
> On Tue, May 17, 2016 at 05:53:56PM -0400, Christopher Friedt wrote:
>> On May 17, 2016 5:49 PM, "Rich Felker" <dalias at libc.org> wrote:
>>> On Tue, May 17, 2016 at 05:46:20PM -0400, Christopher Friedt wrote:
>>>> As it turns out, the reason that the variable was being read back as 0
>>>> was due to the linker script (boot/linker/sh32.x) not having the
>>>> correct location for ram0 (it turned out to be in a completely
>>>> unmapped section of memory - i.e. not in rom and not in sdram @
>>> That's intentional; the address it's using is in SRAM, not DRAM. For
>>> emulating J2, qemu should map that range with writable memory.
>> Sure - what is the actual memory map for the J2 on e.g. the Mimas V2? So
>> far I've only been able to piece it together from fragments. I guess I
>> should probably check the vhdl 8-/
> See Rob's previous post to this list:
> I think the SRAM part is larger than he stated though; check the VHDL
> or just use the boot loader linker script as a guide for now.
It is 32KB. It's all writeable though. There is no ROM/SRAM partition in
the current FPGA designs.
In an ASIC, there will be a separate ROM holding the bootloader and a
writeable RAM region which is uninitialized at power on. At some point
we'll need to implement this same separation between a one-port ROM and
a RAM in the FPGA to test the data and instructions buses work as
expected, but we haven't done that yet even though we'll often call it
If you're curious, the memory is instantiated in the file
soc_top/tools/memory_fpga.vhd.in. This file is modified by a perl
script, soc_top/tools/patchcode.pl, which inserts the INIT_NN generics
into the VHDL to put the bootloader image into the memory. After a
build, look at the resulting memory_fpga.vhd in the output directory to
see it with the initial memory contents included.
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