[J-core] Debugging / JTAG?

[D. Jeff Dionne]

On May 17, 2016, at 7:55 PM, Rob Landley <rob at landley.net> wrote:
> On 05/16/2016 12:33 PM, Christopher Friedt wrote:
>> Hi list,
>> 
>> Is anyone planning on implementing a BSD-licensed JTAG slave
>> controller for J-Core?
> 
> In VHDL? There's half of one but it has timing issues that need fixing.
> (Jeff explained it to me last year, but I don't know the current status
> of it.)

The current implementation of JTAG talks to the Xilinx TAP, and there are problems there (it isn't quite documented properly).  We think we have a solution, since the specific timing bug (or, misunderstanding) was reverse engineered by a project on OpenCores (I don't remember which right now).  Aside from that, there seems to be some issues associated with imprecise state being captured, but this is not certain with the TAP controller giving us one suspect bit at the end of each scan operation...

A proper generic TAP controller that doesn't use the FPGA builtin JTAG machinery is not a big deal to write, it just has to be brought out to some pins...  We need that anyway so it is on the list.

J.

> 
> Rob
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