[J-core] VHDL to silicon pathway?
trayres at gmail.com
Mon Jul 18 12:30:36 EDT 2016
I'm interested in the VHDL to silicon pathway; is there a toolset that's
planned to be used, so I could take a look at it?
I know there's Qflow, but the front end of that is Odin-II, which is a
Verilog parser; what is the planned VHDL parser for synthesis?
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