[J-core] VHDL to silicon pathway?

[D. Jeff Dionne]

We're using a standard (Cadence) flow for a commercial SoC this year at one fab for sure, and test chips for 3 other fabs that have been expressing interest for other customers.

Yes plan is, fully opensource flow looks likely to use QFlow, but with yosys, not Odin-II.  nvc as the vhdl language front end.  We have not had -any- time to work on that of late.  Nick was able to improve nvc, which will now parse and sim j-core RTL (with a few small changes) cycle exact against ghdl.

Cheers,
J.

> On Jul 18, 2016, at 12:30, Travis Ayres <trayres at gmail.com> wrote:
> 
> I'm interested in the VHDL to silicon pathway; is there a toolset that's planned to be used, so I could take a look at it? 
> 
> I know there's Qflow, but the front end of that is Odin-II, which is a Verilog parser; what is the planned VHDL parser for synthesis?
> 
> Thanks,
> -Travis
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