[J-core] Linux on J1?

Rich Felker dalias at libc.org
Tue Aug 2 18:37:38 EDT 2016

On Tue, Aug 02, 2016 at 05:02:45PM -0500, Rob Landley wrote:
> On 08/02/2016 03:38 PM, Rich Felker wrote:
> >> But I thought Niishii-san implemented cmpxchg using some of the existing
> >> cache line invalidation logic?
> > 
> > There's a minimal interaction of cas.l with the dcache when it's
> > enabled, mainly to make sure there are no intervening changes between
> > the compare and the swap I think. But this is not using cache to
> > implement cas.l; it's just making the cache behave correctly with
> > respect to locked operations from one core.
> > 
> > I've proposed that we could weaken the memory model by switching the
> > dcache snoop logic not to invalidate lines when the other core writes,
> > but rather just flag them for invalidation at the time of the next
> > cas.l.
> Then how do atomic writes work ala RCU?

With a very weak memory model (IIRC only Alpha is this weak), either
an explicit barrier is needed in the reader, or the writer needs to
IPI-broadcast barriers onto all other cores. Most weak-memory-order
archs are still sufficiently strong that this kind of thing is not
needed, however. I haven't worked out if additional logic would be
needed to guarantee this minimal level of strength.


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