[J-core] Linux on J1?
dalias at libc.org
Tue Aug 2 16:38:01 EDT 2016
On Tue, Aug 02, 2016 at 03:14:02PM -0500, Rob Landley wrote:
> On 08/02/2016 01:59 PM, D. Jeff Dionne wrote:
> > On Aug 2, 2016, at 11:06, Rich Felker <dalias at libc.org> wrote:
> >> Disabling dcache is a huge hit to performance. It might be more practical to do a
> >> shared-dcache implementation for SMP, where both cores are accessing
> the same cache
> >> (even if subject to stalls when both access it at the same time) that
> would allow
> >> all the snooping logic (and half of the cache memory size) to be omitted.
> > Also, combined I and D cache. There is an instruction prefetcher in the repo that
> > shows just how far you can go without cache, and it's surprisingly far...
> But I thought Niishii-san implemented cmpxchg using some of the existing
> cache line invalidation logic?
There's a minimal interaction of cas.l with the dcache when it's
enabled, mainly to make sure there are no intervening changes between
the compare and the swap I think. But this is not using cache to
implement cas.l; it's just making the cache behave correctly with
respect to locked operations from one core.
I've proposed that we could weaken the memory model by switching the
dcache snoop logic not to invalidate lines when the other core writes,
but rather just flag them for invalidation at the time of the next
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