[J-core] Adding new targets for J2

[Geoff Salmon]

Hi Santiago

The only example board in the open source release is a Spartan 6 one, 
but there are Kintex 7 specific VHDL architectures and VHDL 
configurations for some entities in the release (eg. 
components/clk/clkin25_clkgen_k7.vhd, lib/hwutils/ddr_output_fpga.vhd. 
We have some boards internally that use these Kintex 7 architectures to 
produce Kintex 7 bitstreams.

If you haven't already, take a look at the 
soc_top/targets/boards/mimas_v2/design.edn file. This file tells the 
soc_gen tool what to instantiate and how to wire together the soc in the 
generated vhdl. We don't have much documentation for this, but please 
see my earlier email 
http://lists.j-core.org/pipermail/j-core/2016-April/000070.html for a 
longer description.

If you were to change the first line of the mimas_v2/design from

{:target :spartan6

to

{:target :kintex7


and change line 130 from

                                    :configuration "ddr_phy_spartan6"
to
                                    :configuration "ddr_phy_kintex7"

and then rerun soc_gen (the bottom of soc_top/README describes how to 
run it and the dependencies), then... very little will change in the 
generated vhdl. The only difference would be in 
soc_top/targets/boards/mimas_v2/pad_ring.vhd where instead of instantiating

     ddr_iocells : configuration work.ddr_phy_spartan6

it would instantiate

     ddr_iocells : configuration work.ddr_phy_kintex7

This instantiation of the appropriate architecture or configuration is 
the first step in switching to a different FPGA family. In this case, 
switching :target from :spartan6 to :kintex7 didn't do anything, but it 
may do something in the future.

Unlike the components/clk/clkin10_clkgen.vhd and clkin25_clkgen.vhd, we 
do not have a Kintex7 version of the pll_250 and ddr_clkgen entities 
that generate the clocks in the mimas_v2 board. Depending on the input 
frequency of the clock on your board and the needs of your custom IP, 
you might need custom entities for this anyway. In the mimas_v2 board, 
clk_sys is 50MHz, clk_sys_90 is 50MHz shifted 90 degrees, and clk_sys_2x 
is 100MHz. On a Kintex7, you can likely increase these frequencies a 
bit, and it's possible to increase the frequency of the ddr ram clock 
higher than the cpu clock, but you probably should start with these same 
50, 50, 100 frequencies to start.

The largest part of the job of adding a new board, whether it's Kintex7 
or Spartan6, is going to be making the .pins file that lists the names 
and pad locations of all the FPGA pins you care about and then 
connecting the pins to the appropriate signals in the design.edn file.

See soc_top/targets/pins/mimas_v2.pins for an example of a pins file. 
This one was hand-written. The soc_gen tool will also accept text files 
exported from the eagle pcb design software. If you have some other file 
listing the pins of your board in a machine-readable format, we should 
be able to add it as another format soc_gen will read.

Once soc_gen reads a pins file, the design.edn specifies how to connect 
those pins to signals within the SoC. At the top of mimas_v2/design.edn, 
there is a list of "rules"

:pins { :rules [ <-- list of rules here --> ] }

The :match string in each rule matches pin names from the .pins file. 
For example, this rule

          {:match "mcb3_dram_cas_n" :signal "ddr_sd_ctrl.cas"}

tells soc_gen to connect the pin mcb3_dram_cas_n to a signal which is 
actually a field inside a signal record. You'll need to make sure the 
signals are connected up to the correct pins on your board. One approach 
might be to make the .pins file for your board name use the same pins 
names that the mimas_v2 does. Alternatively, if you're exporting your 
.pins file from some other tool, then you'll likely want to change the 
design.edn to use those names, so that it is referring to pin or net 
names that are meaningful on your board. What Kintex7 board are you using?


For including your own custom IP, you can put the relevant vhdl files in 
soc_top somewhere and either list them in an existing build.mk file, or 
add them in a new directory and create a new build.mk file listing them. 
Look at an existing build.mk for an example. If you add a new one, 
you'll need to edit soc_top/Makefile to include that build.mk. For 
example, if you create soc_top/components/custom/build.mk then add

COMPONENTS += custom

to the list at the top of soc_top/components. In future we want to 
provide hooks in the build system for including VHDL from outside 
soc_top, but those hooks aren't implemented yet.

Once you've done this, your vhdl will be visible to both soc_gen and the 
xilinx ise bitstream builds. To experiment with adding it to the 
mimas_v2 board try adding

"custom" {:entity "custom_entity_name"}

inside the :top-entities map in soc_top/targets/boards/mimas_v2/design.edn

:top-entities { <-- add here --> }

and then rerun soc_gen. You'll probably get an error saying some ports 
of your entity are unconnected. I explain more about connecting ports to 
signals and pins in the email referenced above 
http://lists.j-core.org/pipermail/j-core/2016-April/000070.html

How to proceed from there depends a lot of what your entity's ports are. 
For example if it needs to connect to the cpu data buses or needs an irq 
line then that requires some more changes to the edn. If it does go on 
the data bus, you'll likely need to write a wrapper entity which 
converts between our data bus record types and your own. What sort ports 
does your IP block have?

- Geoff

On 16-06-10 05:44 PM, Gutierrez, Santiago wrote:
> Hi all,
>
> I had previously emailed the OPF email asking if there was a proven way
> to target a new FPGA for the J2 bitstream build. They linked me to
> j-core and I looked through your website as well as the archived mailing
> list. However I couldn’t find a suitable solution for what I am trying
> to do. I would like to specify the Xilinx Kintex 7 as a new build target
> for the J2. I had through the tutorials for using on the microboard, but
> nothing stuck out to me on how to target a new FPGA. I would also like
> to include some custom IP that I have in the bitstream, so someway to
> include that in the build would be great to know. If I’m missing
> something obvious that could help me out on the website, I apologize,
> but any info would help immensely.
>
> Thank you for your time,
>
> Santiago Gutierrez
>
>
>
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