[J-core] Adding new targets for J2

[Geoff Salmon]

Hi Santiago

On 06/13/2016 12:09 PM, Gutierrez, Santiago wrote:
> Hello Geoff and Rob,
>
> Thank you for taking the time to give me all these sources as well as the help. As to the Kintex Board, I am using the standard Kintex 7 Evaluation Board that Xilinx provides.

Is it the Xilinx Kintex-7 FPGA KC705 Evaluation Kit?

> It is just a temporary testing environment however, I will be using the techniques I learn on it on different FPGA's. The IP I will be working with will mostly be the Xilinx provided IP cores for different peripherals, although they will most likely have wrapper hardware for ease of use, so I cannot say for certain what kind of ports they will have.
>
> Although I will be working with the Kintex 7  right now, I will most likely be porting the J2 core onto multiple different FPGA's and am looking for a quick way of porting them over. I was thinking I'd write a script that could do this all, but I am not sure how long that would take. As such I was wondering if you guys could tell me what files are the actual VHDL files for the J2 processor, so that I could isolate them and perhaps work with just the J2 core directly from Xilinx Vivado.

The J2 processor related VHDL is all under soc_top/components/cpu, 
mostly in cpu/core and cpu/decode.

I haven't personally used Vivado. We build with the ISE command line 
tools. The makefile snippet that drives the ISE tools is 
soc_top/tools/xilinx.mk. xilinx_ise.mk would be a more appropriate name, 
and in future there could be a xilinx_vivado.mk that uses Vivado 
instead. It wouldn't be a drop-in replacement, because I think the ucf 
files also need to be replaced with something else for Vivado. Are there 
other things that need to change to use Vivado coming from ISE?

- Geoff