[J-core] What is the correct way to reset the CPU?

[D. Jeff Dionne]

On Jul 18, 2016, at 18:55, Rob Landley <rob at landley.net> wrote:
> 
> Are you referring to the way the FPGA version repurposes some SRAM to act like a boot rom,

Yes,
> and has circuitry that loads initial values into it
> on power on?

At FPGA configuration, which is of course done at power on.
> That circuitry isn't getting called again on reset?

No, not at reset of the RTL design.  It does happen if you reset the fpga, which then loads it's configuration again.
> 
> (I thought the ASICs would have actual boot ROM?)

Yes, correct.  It also doesn't have a configuration (in that case, it would be loading SRAM contents), unless we specifically design and include a state machine to do that.

The result is the fpga doesn't model reset exactly the way a std cell ASIC will behave, because the SRAMs (and any flops with unconnected or improperly timed reset inputs, for that matter) will be initialised (previous contents, or patterns that depend on physical imbalances between the transistors, etc).  We need to separate the SRAM and ROM, even in fpga by using a ram as rom (write port disconnected).

The worst mismatch with ASIC behaviour, but which we can model somewhat by using a normal pin as a 'reset', is asynchronous behaviour, where some flops reset on one clock cycle, and others on a different cycle, so reset has to have an internal state machine to ensure the correct sequencing (which the fpga normally makes happen for you automatically).
> 
> Rob