[J-core] How crazy would a nommu debian port be?

[D. Jeff Dionne]

On Aug 20, 2016, at 2:12 PM, Rob Landley <rob at landley.net> wrote:

> I saw Jeff grab an HDMI demo off the net and stick it in a turtle board to
> make a pretty test pattern we could see on a monitor, demonstrating that
> the HDMI port was wired up properly.

That is just trivial code, the only 'hard' part is the TMDS encoding, which
is only hard because one needs to find documentation on it.  So that simple
code (attached) shows how to do it, and a translation to VHDL for Turtle
might be a good exercise for someone.  The right way might be to make a
function called to_tmds() in a package (not an entity, directly translated
from the Verilog module), and put the registers in the calling entity...

Anyway, notice how tiny the design is, and it likely doesn't even need to be
this big:

Selected Device : 6slx25csg324-3 


Slice Logic Utilization: 
 Number of Slice Registers:             124  out of  30064     0%  
 Number of Slice LUTs:                  234  out of  15032     1%  
    Number used as Logic:               234  out of  15032     1%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    287
   Number with an unused Flip Flop:     163  out of    287    56%  
   Number with an unused LUT:            53  out of    287    18%  
   Number of fully used LUT-FF pairs:    71  out of    287    24%  
   Number of unique control sets:         7

IO Utilization: 
 Number of IOs:                           9
 Number of bonded IOBs:                   9  out of    226     3%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  

> But it wasn't doing DMA from a framebuffer, it was just generating a
> pattern based off of a timer and some registers. (And it was verilog
> while what we're doing is vhdl, and who knows what the license was. At
> the moment the plan to implement the hdmi video support for turtle is
> still "write new vhdl code".)

It really only takes a few hours to implement the DMA, instead of a few patters
based on X and Y once the timing generation is in place...  I've also attached
the .ucf for this demo also, and note that the Verilog directly instantiates
the Xilinx DCM clock generator... that's a real no-no, please don't do that.

J

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