[J-core] j-core.org roadmap.

Rob Landley rob at landley.net
Tue May 18 02:13:22 UTC 2021

On 5/17/21 4:31 PM, D. Jeff Dionne wrote:
> On May 17, 2021, at 12:23, Rob Landley <rob at landley.net
> <mailto:rob at landley.net>> wrote:
>> Hmmm, this is an old Hitachi glossy flyer on another fly-by-night site that
>> could be 404 again in a couple years.
>> http://www.ic72.com/pdf_file/h/244158.pdf
> This is actually a flyer for (what became) System In Package 'chips'.  Note the
> inclusion of SDRAM in the example SIP device in this flyer.
> Some years ago before J-Core (and before Renesas, actually) we did some Voice
> over IP projects, including a small bump-in-the-wire size analog terminal
> adapter.  Hitachi did a SIP for us with IIRC a 7713 SH3 device and an SDRAM, but
> it never went to market.  Later versions included the 7619 SH2 based device, but
> that wasn't integrated into a SIP.
> Fast forward to today, and on the small end of things, some micro controllers
> are actually the combination of a SPI FLASH with a die that has no FLASH, and
> therefore requires nothing but a standard logic process.
>  https://zeptobars.com/en/read/GD32F103CBT6-mcm-serial-flash-Giga-Devices  A lot
> simpler than Hitachi's mutichip modules or SIP, but really effective.

Isn't that what we were proposing to do? Hence the spi fetcher hardware thing
that got abandoned because of cache aliasing or some such?

Anyway, my question is more along the lines of "if I don't upload the PDF to
j-core, how do I refer to this stuff?"


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