[J-core] Happy new year.

[D. Jeff Dionne]

On Jan 10, 2021, at 17:07, Daniel G. <giri at nwrk.biz> wrote:

> Hello and Happy new year,

Happy New Year.

> Can you confirm me that synthesis of the SoC for fpgas other than Xilinx is currently not possible due to the usage of unisim.vcomponents for some parts of the SoC.

No, this is incorrect.  unisim.vcomponents is not used in the SoC design.  Of course Xilinx specific IO and clock cells are instantiated, on Xilinx platforms... and the equivalents are instantiated on other platforms (ASIC or e.g. Lattice).

The design itself is portable.

Cheers,
J.

> 
> -- 
> Kind regards,
> Daniel G.

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